The first production and packaging details about AMD’s new generation processors with Zen 7 architecture have emerged. According to the report originating from Taiwan, the Zen 7 CCD design, codenamed Grimlock, will use TSMC’s A14, or 1.4 nm class, production process. In the same report, the new generation 3D V-Cache technology and Powertech’s FOPLP packaging solution are also mentioned together with AMD’s future processor plans.
A 2028 calendar is being discussed for Zen 7 Grimlock
AMD had previously included the Zen 7 architecture in its official road map. The road map shared by the company includes Future Node and Next-Generation expressions for Zen 7. It has been previously shown that this architecture will feature the new Matrix Engine and AI data format expansion. However, the production process, code name, core structure and cache details have not yet been officially announced by AMD.
According to the new report, the CCD to be used in Zen 7-based processors is being prepared with the code name Grimlock. On the CCD side, the TSMC A14 production process is mentioned. TSMC’s A14 technology is included in the company’s new advanced production family after the N2 process and is planned to enter production in 2028.
TSMC announced a speed increase of up to 15 percent at the same power or a power consumption decrease of up to 30 percent at the same speed and an increase in logic density of over 20 percent for the A14 compared to the N2. Another notable title for Zen 7 was the new generation 3D V-Cache. The report states that the standard L3 cache and 3D V-Cache capacity will be increased in the Zen 7-based CCD design.
The transferred information includes a claim of up to 224 MB L3 cache on a single 3D V-Cache CCD. This detail is not official AMD data for now, but it is among the important claims that Zen 7 can switch to a more aggressive design, especially for desktop and server workloads that require high cache.
On the packaging side, Powertech’s FOPLP technology came to the fore. FOPLP is used as an abbreviation for Fan-Out Panel-Level Packaging. Unlike traditional round wafer-based production, the panel-level packaging approach can provide larger production area and potential cost advantages. This technology is gaining more importance especially in processor designs that require multiple chips, high bandwidth and advanced connectivity.
The report also states that AMD CEO Lisa Su contacted Powertech during her visit to Taiwan and that this meeting was related to advanced packaging capacity. It is known that AMD has been using chiplet design in its Zen architectures for a long time. For this reason, in the Zen 7 era, not only the production process, but also the packaging and inter-chip connection structure will be one of the determining topics in terms of performance and efficiency.
The calendar on the TSMC side also points to the same period as these claims. The company placed the A14 process in the 2028 production schedule, while the A13 process was placed in the 2029 schedule as a direct scaled-down continuation of the A14. TSMC also announced A12 platform development for 2029.
AMD’s Zen 6 architecture has yet to fully hit mainstream server and consumer products. Zen 6’s transition to the 2 nm class production process and Zen 7’s positioning at the next node show that the company is accelerating the production technology transition in its multi-year road map.
Since Zen 7 will feature the new Matrix Engine and AI data format expansion, the architecture is expected to bring changes that directly touch not only classic CPU performance but also artificial intelligence and data center workloads.
Comments
You can write your views about this story. Comments may be moderated according to site settings.